1. Field of the Invention
The present invention relates to a solid state image sensing device provided with a column AD converter.
2. Description of the Related Art
In recent years, a solid state image sensing device incorporated with a CMOS (Complementary Metal Oxide Semiconductor) image sensor provided with a column A/D converter has been widely spread. For instance, there is known a solid state image sensing device including a pixel array constituted of pixels arranged in a matrix of a predetermined number of rows and a predetermined number of columns; and column A/D converting circuits corresponding to the columns of the pixel array, and for reading out a pixel signal from the pixel array for A/D conversion. Each of the column A/D converting circuits is a double integral A/D converting circuit for dividing the pixel signal into two blocks, and performing A/D conversion with respect to the blocks (see Japanese Unexamined Patent Publication No. 2002-232291).
FIG. 9 is a circuit diagram showing a column A/D converting circuit, corresponding to one column, to be used in a conventional solid state image sensing device. The column A/D converting circuit shown in FIG. 9 is a single slope integration column A/D converting circuit, and includes, in the order of input of a pixel signal from a pixel array, a GCA (Gain Control Amplifier) section 100, a comparator section 200, a logic circuit 300, a latch section 400, and a switch section 500.
The GCA section 100 is operable to amplify a pixel signal outputted from the pixel array, while performing CDS (Correlated Double Sampling) to remove a noise signal from the pixel signal.
The comparator section 200 has two comparators provided stepwise, and is operable to compare a pixel signal outputted from the GCA section 100 with two ramp signals (hereinafter, called as ramp signals Ramp1 and Ramp2). The ramp signal Ramp1 stepwise decreases in four steps, as time elapses, and the ramp signal Ramp2 stepwise increases in four steps, as time elapses.
The comparator section 200 compares the pixel signal outputted from the GCA section 100, with the ramp signal Ramp1 for A/D conversion with respect to upper two bits of the pixel signal; and inverts the output signal, if the level of the ramp signal Ramp1 is under the level of the pixel signal. After the comparison between the ramp signal Ramp1 and the pixel signal is terminated, the comparator section 200 compares the pixel signal outputted from the GCA section 100, with the ramp signal Ramp2 for A/D conversion with respect to lower two bits of the pixel signal; and inverts the output signal, if the level of the ramp signal Ramp2 is over the level of the pixel signal.
In response to inversion of the output signal by the comparator section 200, as a result of comparison between the pixel signal and the ramp signal Ramp1, the logic circuit 300 sets a signal COMPOUT1 to COMPOUT1=L (low level), and outputs the signal to a latch circuit 410. In response to inversion of the output signal by the comparator section 200, as a result of comparison between the pixel signal and the ramp signal Ramp2, the logic circuit 300 sets a signal COMPOUT2 to COMPOUT2=L, and outputs the signal to a latch circuit 420.
A counter 710 is constituted of a two-bit counter provided at the exterior of the column A/D converting circuit, and starts a counting operation in response to input of the ramp signal Ramp1 to the comparator section 200. Likewise, a counter 720 is constituted of a two-bit counter provided at the exterior of the column A/D converting circuit, and starts a counting operation in response to input of the ramp signal Ramp2 to the comparator section 200.
The latch section 400 includes the latch circuit 410 and the latch circuit 420. The latch circuit 410 latches a currently counted value of the counter 710, when COMPOUT1=L. Thereby, the latch circuit 410 latches digital data of upper two bits of the A/D converted pixel signal.
Likewise, the latch circuit 420 latches a currently counted value of the counter 720, when COMPOUT2=L. Thereby, the latch circuit 420 latches digital data of lower two bits of the A/D converted pixel signal.
A horizontal scanning circuit 600 outputs a column selecting signal indicating a column to be sequentially selected to switches 510 and 520, upon completion of A/D conversion with respect to the upper two bits of the pixel signal and the lower two bits of the pixel signal, turns on the switches 510 and 520, and outputs the digital data of upper two bits latched by the latch circuit 410, and the digital data of lower two bits latched by the latch circuit 420 to a horizontal signal line.
FIG. 10 is a timing chart of the column A/D converting circuit shown in FIG. 9. The timing chart shows operations to be performed with respect to a pixel signal at the i-th row of a pixel array in one horizontal scanning period.
Referring to FIG. 10, the symbol Vpixel indicates a pixel signal to be inputted to the GCA section 100, φPRST indicates a signal for turning on and off a switch of the GCA section 100, φS1 indicates a signal for turning on and off a switch of the former comparator in the comparator section 200, φS2 indicates a signal for turning on and off a switch of the latter comparator in the comparator section 200, φSH indicates a signal for turning on and off a switch connected between the GCA section 100 and the comparator section 200, φCK1 indicates a signal to be inputted to the upper NAND gate in the logic circuit 300, φCK2 indicates a signal to be inputted to the lower NAND gate in the logic circuit 300, Counter 1 indicates a counted value of the counter 710, Counter 2 indicates a counted value of the counter 720, Horizontal Shift Register Start Pulse indicates a horizontal synchronizing signal representing start of one horizontal scanning period, and DATAOUT indicates digital data to be outputted from the latch circuits 410 and 420.
As shown in FIG. 10, in one horizontal scanning period, the following operations (1) through (3) are performed, and the following operation (4) is performed concurrently with the operations (1) through (3).
Operation (1): Pixel readout (i-th row) An operation of reading out a pixel signal at the i-th row, while performing CDS to remove a noise signal from the pixel signal.
Operation (2): Upper bit A/D conversion (i-th row) An operation of performing A/D conversion with respect to upper two bits of the pixel signal at the i-th row.
Operation (3): Lower bit A/D conversion (i-th row) An operation of performing A/D conversion with respect to lower two bits of the pixel signal at the i-th row.
Operation (4): Output ((i−1)-th row) An operation of outputting the A/D converted pixel signal at the (i−1)-th row.
As shown in FIG. 9, the latch section 400 has a two-step arrangement constituted of the latch circuit 410 and the latch circuit 420. Accordingly, the operations (1) through (3), and the operation (4) can be concurrently performed. Specifically, digital data of the pixel signal at the (i−1)-th row can be outputted, while performing A/D conversion with respect to the pixel signal at the i-th row.
If the level of the ramp signal Ramp1 is under the level of the pixel signal at a timing TM1 in the period of the operation (2), COMPOUT1=L. Since the counted value of the Counter 1 when COMPOUT1=L is “01”, the latch circuit 410 latches “01”.
If the level of the ramp signal Ramp2 is over the level of the pixel signal at a timing TM2 in the period of the operation (3), COMPOUT2=L. Since the counted value of the Counter 2 when COMPOUT2=L is “10”, the latch circuit 420 latches “10”.
Then, in a succeeding horizontal scanning period, “01” latched by the latch circuit 410, and “10” latched by the latch circuit 420 are outputted to the horizontal signal line.
As described above, the double integral A/D converting circuit having the above arrangement enables to perform A/D conversion with a less number of clocks. Accordingly, as compared with a single integral A/D converting circuit, a time required for A/D conversion can be reduced, and one horizontal scanning period can be reduced. Thereby, the frame rate can be increased, and a high-speed photographing operation can be performed.
FIG. 11 is a sequence diagram on pixel signals at the i-th row and the (i+1)-th row to be processed by the A/D converting circuit shown in FIG. 9. The operations (1) through (3) are performed in one horizontal scanning period for the first row, wherein the pixel signal at the i-th row is subjected to A/D conversion, and the A/D converted digital data is latched by the latch circuits 410 and 420.
Then, in one horizontal scanning period for the second row, the operations (1) through (3) are performed, wherein the pixel signal at the (i+1)-th row is subjected to A/D conversion, and the A/D converted digital data is latched by the latch circuits 410 and 420; and the operation (4) is also performed, wherein the digital data of the i-th row latched by the latch circuits 410 and 420 is outputted from the latch circuits 410 and 420.
Then, in one horizontal scanning period for the third row, the operation (4) is performed, wherein the digital data of the (i+1)-th row latched by the latch circuits 410 and 420 is outputted from the latch circuits 410 and 420.
Specifically, in each of the one horizontal scanning periods, A/D conversion of the pixel signal at the (i+1)-th row, and output of the pixel signal at the i-th row are concurrently performed.
In the case where a pixel signal is divided into data of upper two bits and data of lower two bits for A/D conversion, as implemented by the A/D converting circuit shown in FIG. 9, the computation result on digital data of upper two bits is important. A/D conversion with respect to data of upper two bits is performed based on a comparison result between the ramp signal Ramp1 and the pixel signal. However, a certain time is required until the ramp signal Ramp1 is completely settled. In view of this, it is necessary to secure a predetermined time as a period for A/D conversion with respect to data of upper two bits in order to perform high-precision A/D conversion with respect to data of upper two bits.
As shown in FIG. 11, the operations (1) through (3) are performed in one horizontal scanning period by the A/D converting circuit shown in FIG. 9. It is, however, difficult to reduce the time required for performing the operation (2) of performing A/D conversion with respect to data of upper two bits. Accordingly, in the above arrangement, it is impossible to reduce one horizontal scanning period, and increase the frame rate.